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ddr3 sdram rdimm mt36jc(z)s1g72py C 8gb features ? ddr3 functionality and operations supported as defined in the component data sheet ? 240-pin, registered dual in-line memory module (rdimm) ? fast data transfer rates: pc3-12800, pc3-10600, pc3-8500, or pc3-6400 ? 8gb (1 gig x 72) ? full module heat spreader ? v dd = 1.5v 0.075v ? v ddspd = +3.0v to +3.6v ? supports ecc error detection and correction ? nominal and dynamic on-die termination (odt) for data and strobe signals ? dual rank, using 4gb twindie ? devices ? on-board i 2 c temperature sensor with integrated serial presence-detect (spd) eeprom ? 8 internal device banks ? fixed burst chop (bc) of 4 and burst length (bl) of 8 via the mode register set (mrs) ? selectable bc4 or bl8 on-the-fly (otf) ? gold edge contacts ? lead-free ? fly-by topology ? terminated control, command, and address bus figure 1: 240-pin low-profile rdimm module height: 19.5mm (0.768in) options marking ? heat spreader C without heat spreader jcs C with heat spreader jczs ? operating temperature C commercial (0c t a +70c) none ? package C 240-pin dimm (lead-free) y ? frequency/cas latency C 1.25ns @ cl = 11 (ddr3-1600) -1g6 C 1.5ns @ cl = 9 (ddr3-1333) -1g4 C 1.87ns @ cl = 7 (ddr3-1066) -1g1 table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 11 cl = 10 cl = 9 cl = 8 cl = 7 cl = 6 cl = 5 -1g6 pc3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125 -1g4 pc3-10600 C 1333 1333 1066 1066 800 667 13.125 13.125 49.125 -1g1 pc3-8500 C C C 1066 1066 800 667 13.125 13.125 50.625 -1g0 pc3-8500 C C C 1066 C 800 667 15 15 52.5 -80b pc3-6400 C C C C C 800 667 15 15 52.5 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm features pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 8gb refresh count 8k row address 32k a[14:0] device bank address 8 ba[2:0] device configuration 4gb twindie (1 gig x 4) column address 2k a[11, 9:0] module rank address 2 s#[1:0] table 3: part numbers and timing parameters C 2gb modules base device: mt41j1g4thu, 1 4gb twindie ddr3 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt36jc(z)s1g72py-1g6__ 8gb 1 gig x 72 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 mt36jc(z)s1g72py-1g4__ 8gb 1 gig x 72 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 mt36jc(z)s1g72py-1g1__ 8gb 1 gig x 72 8.5 gb/s 1.87ns/1066 mt/s 7-7-7 notes: 1. the data sheet for the base device can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. consult factory for current revision codes. example: mt36jczs1g72py-1g1 d1. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm features pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
pin assignments table 4: pin assignments 240-pin ddr3 rdimm front 240-pin ddr3 rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 v refdq 31 dq25 61 a2 91 dq41 121 v ss 151 v ss 181 a1 211 v ss 2 v ss 32 v ss 62 v dd 92 v ss 122 dq4 152 dqs12 182 v dd 212 dqs14 3 dq0 33 dqs3# 63 nf 93 dqs5# 123 dq5 153 dqs12# 183 v dd 213 dqs14# 4 dq1 34 dqs3 64 nf 94 dqs5 124 v ss 154 v ss 184 ck0 214 v ss 5 v ss 35 v ss 65 v dd 95 v ss 125 dqs9 155 dq30 185 ck0# 215 dq46 6 dqs0# 36 dq26 66 v dd 96 dq42 126 dqs9# 156 dq31 186 v dd 216 dq47 7 dqs0 37 dq27 67 v refca 97 dq43 127 v ss 157 v ss 187 event# 217 v ss 8 v ss 38 v ss 68 par_in 98 v ss 128 dq6 158 cb4 188 a0 218 dq52 9 dq2 39 cb0 69 v dd 99 dq48 129 dq7 159 cb5 189 v dd 219 dq53 10 dq3 40 cb1 70 a10 100 dq49 130 v ss 160 v ss 190 ba1 220 v ss 11 v ss 41 v ss 71 ba0 101 v ss 131 dq12 161 dqs17 191 v dd 221 dqs15 12 dq8 42 dqs8# 72 v dd 102 dqs6# 132 dq13 162 dqs17# 192 ras# 222 dqs15# 13 dq9 43 dqs8 73 we# 103 dqs6 133 v ss 163 v ss 193 s0# 223 v ss 14 v ss 44 v ss 74 cas# 104 v ss 134 dqs10 164 cb6 194 v dd 224 dq54 15 dqs1# 45 cb2 75 v dd 105 dq50 135 dqs10# 165 cb7 195 odt0 225 dq55 16 dqs1 46 cb3 76 s1# 106 dq51 136 v ss 166 v ss 196 a13 226 v ss 17 v ss 47 v ss 77 odt1 107 v ss 137 dq14 167 nc 197 v dd 227 dq60 18 dq10 48 v tt 78 v dd 108 dq56 138 dq15 168 reset# 198 nc 228 dq61 19 dq11 49 v tt 79 nc 109 dq57 139 v ss 169 cke1 199 v ss 229 v ss 20 v ss 50 cke0 80 v ss 110 v ss 140 dq20 170 v dd 200 dq36 230 dqs16 21 dq16 51 v dd 81 dq32 111 dqs7# 141 dq21 171 a15 201 dq37 231 dqs16# 22 dq17 52 ba2 82 dq33 112 dqs7 142 v ss 172 a14 202 v ss 232 v ss 23 v ss 53 err_out# 83 v ss 113 v ss 143 dqs11 173 v dd 203 dqs13 233 dq62 24 dqs2# 54 v dd 84 dqs4# 114 dq58 144 dqs11# 174 a12 204 dqs13# 234 dq63 25 dqs2 55 a11 85 dqs4 115 dq59 145 v ss 175 a9 205 v ss 235 v ss 26 v ss 56 a7 86 v ss 116 v ss 146 dq22 176 v dd 206 dq38 236 v ddspd 27 dq18 57 v dd 87 dq34 117 sa0 147 dq23 177 a8 207 dq39 237 sa1 28 dq19 58 a5 88 dq35 118 scl 148 v ss 178 a6 208 v ss 238 sda 29 v ss 59 a4 89 v ss 119 sa2 149 dq28 179 v dd 209 dq44 239 v ss 30 dq24 60 v dd 90 dq40 120 v tt 150 dq29 180 a3 210 dq45 240 v tt 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm pin assignments pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
pin descriptions the pin description table below is a comprehensive list of all possible pins for all ddr3 modules. all pins listed may not be supported on this module. see pin assignments for information specific to this module. table 5: pin descriptions symbol type description ax input address inputs: provide the row address for active commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by bax) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. see the pin assignments table for density-specific addressing information. bax input bank address inputs: define the device bank to which an active, read, write, or precharge command is being applied. ba define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ckx, ckx# input clock: differential clock inputs. all control, command, and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. ckex input clock enable: enables (registered high) and disables (registered low) internal circui- try and clocks on the dram. dmx input data mask (x8 devices only): dm is an input mask signal for write data. input data is masked when dm is sampled high, along with that input data, during a write ac- cess. although dm pins are input-only, dm loading is designed to match that of the dq and dqs pins. odtx input on-die termination: enables (registered high) and disables (registered low) termi- nation resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to the following pins: dq, dqs, dqs#, dm, and cb. the odt input will be ignored if disabled via the load mode command. par_in input parity input: parity bit for ax, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input (lvcmos) reset: reset# is an active low asychronous input that is connected to each dram and the registering clock driver. after reset# goes high, the dram must be reinitial- ized as though a normal power-up was executed. sx# input chip select: enables (registered low) and disables (registered high) the command decoder. sax input serial address inputs: used to configure the temperature sensor/spd eeprom ad- dress range on the i 2 c bus. scl input serial clock for temperature sensor/spd eeprom: used to synchronize communi- cation to and from the temperature sensor/spd eeprom on the i 2 c bus. cbx i/o check bits: used for system error detection and correction. dqx i/o data input/output: bidirectional data bus. dqsx, dqsx# i/o data strobe: differential data strobes. output with read data; edge-aligned with read data; input with write data; center-aligned with write data. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm pin descriptions pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 5: pin descriptions (continued) symbol type description sda i/o serial data: used to transfer addresses and data into and out of the temperature sensor/ spd eeprom on the i 2 c bus. tdqsx, tdqsx# output redundant data strobe (x8 devices only): tdqs is enabled/disabled via the load mode command to the extended mode register (emr). when tdqs is enabled, dm is disabled and tdqs and tdqs# provide termination resistance; otherwise, tdqs# are no function. err_out# output (open drain) parity error output: parity error found on the command and address bus. event# output (open drain) temperature event: the event# pin is asserted by the temperature sensor when crit- ical temperature thresholds have been exceeded. v dd supply power supply: 1.5v 0.075v. the component v dd and v ddq are connected to the mod- ule v dd . v ddspd supply temperature sensor/spd eeprom power supply: 3.0C3.6v. v refca supply reference voltage: control, command, and address v dd /2. v refdq supply reference voltage: dq, dm v dd /2. v ss supply ground. v tt supply termination voltage: used for control, command, and address v dd /2. nc C no connect: these pins are not connected on the module. nf C no function: these pins are connected within the module, but provide no functionality. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm pin descriptions pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
dq map table 6: component-to-module dq map component reference number component dq module dq module pin number component reference number component dq module dq module pin number u1 0 3 10 u11 0 60 227 1 1 4 1 62 233 2 2 9 2 61 228 3 0 3 3 63 234 u2 0 11 19 u12 0 52 218 1 9 13 1 54 224 2 10 18 2 53 219 3 8 12 3 55 225 u3 0 19 28 u13 0 44 209 1 17 22 1 46 215 2 18 27 2 45 210 3 16 21 3 47 216 u4 0 27 37 u14 0 36 200 1 25 31 1 38 206 2 26 36 2 37 201 3 24 30 3 39 207 u5 0 cb3 46 u16 0 cb4 158 1 cb1 40 1 cb6 164 2 cb2 45 2 cb5 159 3 cb0 39 3 cb7 165 u7 0 35 88 u17 0 28 149 1 33 82 1 30 155 2 34 87 2 29 150 3 32 81 3 31 156 u8 0 43 97 u18 0 20 140 1 41 91 1 22 146 2 42 96 2 21 141 3 40 90 3 23 147 u9 0 51 106 u19 0 12 131 1 49 100 1 14 137 2 50 105 2 13 132 3 48 99 3 15 138 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm dq map pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
table 6: component-to-module dq map (continued) component reference number component dq module dq module pin number component reference number component dq module dq module pin number u10 0 59 115 u20 0 4 122 1 57 109 1 6 128 2 58 114 2 5 123 3 56 108 3 7 129 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm dq map pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
functional block diagram figure 2: functional block diagram dm cs# dqs dqs# dq dq dq dq zq dq0 dq1 dq2 dq3 v ss dq dq dq dq u1b u1t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq4 dq5 dq6 dq7 v ss dq dq dq dq u20b u20t dm cs# dqs dqs# dqs0 dqs0# dqs9 dqs9# dm cs# dqs dqs# dq dq dq dq zq dq8 dq9 dq10 dq11 v ss dq dq dq dq u2b u2t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq12 dq13 dq14 dq15 v ss dq dq dq dq u19b u19t dm cs# dqs dqs# dqs1 dqs1# dqs10 dqs10# dm cs# dqs dqs# dq dq dq dq zq dq16 dq17 dq18 dq19 v ss dq dq dq dq u3b u3t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq20 dq21 dq22 dq23 v ss dq dq dq dq u18b u18t dm cs# dqs dqs# dqs2 dqs2# dqs11 dqs11# dm cs# dqs dqs# dq dq dq dq zq dq24 dq25 dq26 dq27 v ss dq dq dq dq u4b u4t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq28 dq29 dq30 dq31 v ss dq dq dq dq u17b u17t dm cs# dqs dqs# dqs3 dqs3# dqs12 dqs12# dm cs# dqs dqs# dq dq dq dq zq cb0 cb1 cb2 cb3 v ss dq dq dq dq u5b u5t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq cb4 cb5 cb6 cb7 v ss dq dq dq dq u16b u16t dm cs# dqs dqs# dqs8 dqs8# dqs17 dqs17# dm cs# dqs dqs# dq dq dq dq zq dq32 dq33 dq34 dq35 v ss dq dq dq dq u7b u7t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq36 dq37 dq38 dq39 v ss dq dq dq dq u14b u14t dm cs# dqs dqs# dqs4 dqs4# dqs13 dqs13# dm cs# dqs dqs# dq dq dq dq zq dq40 dq41 dq42 dq43 v ss dq dq dq dq u8b u8t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq44 dq45 dq46 dq47 v ss dq dq dq dq u13b u13t dm cs# dqs dqs# dqs5 dqs5# dqs14 dqs14# dm cs# dqs dqs# dq dq dq dq zq dq48 dq49 dq50 dq51 v ss dq dq dq dq u9b u9t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq52 dq53 dq54 dq55 v ss dq dq dq dq u12b u12t dm cs# dqs dqs# dqs6 dqs6# dqs15 dqs15# dm cs# dqs dqs# dq dq dq dq zq dq56 dq57 dq58 dq59 v ss dq dq dq dq u10b u10t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq zq dq60 dq61 dq62 dq63 v ss dq dq dq dq u11b u11t dm cs# dqs dqs# dqs7 dqs7# dqs16 dqs16# rs0# rs1# zq zq zq zq zq zq zq zq v ss zq zq zq zq zq zq zq zq zq zq r e g i s t e r a n d p l l s0# s1# ba[2:0] a[15:0] ras# cas# we# cke0 cke1 odt0 odt1 par_in reset# ck0 ck0# rs0#: rank 0 rs1#: rank 1 rba[2:0]: ddr3 sdram ra[14:0]: ddr3 sdram rras#: ddr3 sdram rcas#: ddr3 sdram rwe#: ddr3 sdram rcke0: rank 0 rcke1: rank 1 rodt0: rank 0 rodt1: rank 1 err_out# u6 v refca v ss v ss ddr3 sdram ddr3 sdram v dd ddr3 sdram v ddspd temperature sensor/ spd eeprom v tt ddr3 sdram ddr3 sdram v refdq ck ck# ddr3 sdram ddr3 sdram rank 0: u1bCu5b, u7bCu14b, u16bCu20b rank 1: u1tCu5t, u7tCu14t, u16tCu20t v ss rs#[1:0], rcke[1:0], ra[14:0], rras#, rcas#, rwe#, rodt[1:0], rba[2:0] ck ck# clock, command, control, and address line terminations: ddr3 sdram v tt ddr3 sdram v dd u15 a0 temperature sensor/ spd eeprom a1 a2 sa0 sa1 sda scl evt event# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss note: 1. the zq ball on each ddr3 component is connected to an external 240 1% resistor that is tied to ground. it is used for the calibration of the components odt and output driver. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm functional block diagram pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
general description ddr3 sdram modules are high-speed, cmos dynamic random access memory mod- ules that use internally configured 8-bank ddr3 sdram devices. ddr3 sdram mod- ules use ddr architecture to achieve high-speed operation. ddr3 architecture is essentially a 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram module effectively consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corresponding n -bit-wide, one-half-clock-cycle data trans- fers at the i/o pins. ddr3 modules use two sets of differential signals: dqs, dqs# to capture data and ck and ck# to capture commands, addresses, and control signals. differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. fly-by topology ddr3 modules use faster clock speeds than earlier ddr technologies, making signal quality more important than ever. for improved signal quality, the clock, control, com- mand, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each dram is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). inherent to fly-by topology, the timing skew between the clock and dqs signals can be easily accounted for by using the write-leveling feature of ddr3. registering clock driver operation registered ddr3 sdram modules use a registering clock driver device consisting of a register and a phase-lock loop (pll). the device complies with the jedec standard "definition of the sste32882 registering clock driver with parity and quad chip se- lects for ddr3 rdimm applications." the register section of the registering clock driver latches command and address input signals on the rising clock edge. the pll section of the registering clock driver receives and redrives the differential clock signals (ck, ck#) to the ddr3 sdram devices. the register(s) and pll reduce clock, control, command, and address signals loading by iso- lating dram from the system controller. parity operations the registering clock driver includes an even parity function for checking parity. the memory controller accepts a parity bit at the par_in input and compares it with the data received on a[15:0], ba[2:0], ras#, cas#, and we#. valid parity is defined as an even number of ones (1s) across the address and command inputs (a[15:0], ba[2:0], ras#, cas#, and we#) combined with par_in. parity errors are flagged on err_out#. address and command parity is checked during all dram operations and during con- trol word write operations to the registering clock driver. for sdram operations, the address is still propagated to the sdram even when there is a parity error. when writ- ing to the internal control words of the registering clock driver, the write will be ignored if parity is not valid. for this reason, systems must connect the par_in pins on the dimm and provide correct parity when writing to the registering clock driver control word configuration registers. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm general description pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
temperature sensor with serial presence-detect eeprom thermal sensor operations the temperature from the integrated thermal sensor is monitored and converts into a digital word via the i 2 c bus. system designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. pro- gramming and configuration details comply with jedec standard no. 21-c page 4.7-1, "definition of the tse2002av, serial presence detect with temperature sensor." serial presence-detect eeprom operation ddr3 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are programmed by micron to comply with je- dec standard jc-45, "appendix x: serial presence detect (spd) for ddr3 sdram modules." these bytes identify module-specific timing parameters, configuration infor- mation, and physical attributes. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimms scl (clock) sda (data), and sa (address) pins. write protect (wp) is connected to v ss , perma- nently disabling hardware write protection. for further information refer to micron technical note tn-04-42, "memory module serial presence-detect." 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the module. this is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in each device's data sheet is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. table 7: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss C0.4 1.975 v v in , v out voltage on any pin relative to v ss C0.4 1.975 v table 8: operating conditions symbol parameter min nom max units notes v dd v dd supply voltage 1.425 1.5 1.575 v i vtt termination reference current from v tt C600 C +600 ma v tt termination reference voltage (dc) C command/address bus 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v 1 i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address in- puts, ras#, cas#, we#, s#, cke, odt, ba, ck, ck# tbd tbd tbd a i oz output leakage current; 0v v out v dd ; dq and odt are disabled; odt is high dq, dqs, dqs# C10 0 +10 a i vref v ref supply leakage current; v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v) C36 0 +36 a t a module ambient operating temperature commercial 0 C +70 c 2, 3 t c ddr3 sdram compo- nent case operating temperature commercial 0 C +95 c 2, 3, 4 notes: 1. v tt termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. 2. t a and t c are simultaneous requirements. 3. for further information, refer to technical note tn-00-08: thermal applications, available on microns web site. 4. the refresh rate is required to double when 85c < t c 95c. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm electrical specifications pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
dram operating conditions recommended ac operating conditions are given in the ddr3 component data sheets. component specifications are available on microns web site. module speed grades cor- relate with component speed grades, as shown below. table 9: module and component speed grades ddr3 components may exceed the listed module speed grades; module may not be available in all listed speed grades module speed grade component speed grade -1g9 -107 -1g6 -125 -1g4 -15e -1g1 -187e -1g0 -187 -80c -25e -80b -25 design considerations simulations micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good signal integrity starts at the system level. micron encourages designers to simulate the signal characteristics of the system's mem- ory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram, not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm dram operating conditions pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
i dd specifications table 10: ddr3 i cdd specifications and conditions C 8gb values are for the mt41j1g4thu ddr3 sdram only and are computed from values specified in the 4gb twindie (1 gig x 4) component data sheet, die rev d parameter combined symbol 1600 1333 1066 units operating current 0: one bank activate-to- precharge i cdd0 2016 1836 1656 ma operating current 1: one bank activate-to-read-to- precharge i cdd1 2196 2106 2016 ma precharge power-down current: slow exit i cdd2p0 432 432 432 ma precharge power-down current: fast exit i cdd2p1 846 756 666 ma precharge quiet standby current i cdd2q 936 846 756 ma precharge standby current i cdd2n 972 882 792 ma precharge standby odt current i cdd2nt 1116 1026 936 ma active power-down current i cdd3p 936 846 756 ma active standby current i cdd3n 1026 936 846 ma burst read operating current i cdd4r 3276 2916 2556 ma burst write operating current i cdd4w 3366 3096 2736 ma refresh current i cdd5b 4086 3816 3636 ma self refresh temperature current: max t c = 85c i cdd6 432 432 432 ma self refresh temperature current (srt-enabled): max t c = 95c i cdd6et 540 540 540 ma all banks interleaved read current i cdd7 8136 7236 6336 ma reset current i cdd8 504 504 504 ma 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm i dd specifications pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
registering clock driver specifications table 11: registering clock driver electrical characteristics sste32882 devices or equivalent parameter symbol pins min nom max units dc supply voltage v dd C 1.425 1.5 1.575 v dc reference voltage v ref C 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v dc termination voltage v tt C 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v ac high-level input voltage v ih(ac) control, command, address v ref + 175mv C v dd + 400mv v ac low-level input voltage v il(ac) control, command, address C0.4 C v ref - 175mv v dc high-level input voltage v ih(dc) control, command, address v ref + 100mv C v dd + 0.4 v dc low-level input voltage v il(dc) control, command, address C0.4 C v ref - 100mv v high-level input voltage v ih(cmos) reset#, mirror 0.65 v dd C v dd v low-level input voltage v il(cmos) reset#, mirror 0 C 0.35 v dd v differential input crosspoint voltage range v ix(ac) ck, ck#, fbin, fbin# 0.5 v dd - 175mv 0.5 v dd 0.5 v dd + 175mv v differential input voltage v id(ac) ck, ck# 350 C v dd + tbd mv high-level output current i oh err_out# C C tbd ma low-level output current i ol err_out# tbd C tbd ma note: 1. timing and switching specifications for the register listed are critical for proper opera- tion of the ddr3 sdram rdimms. these are meant to be a subset of the parameters for the specific device used on the module. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm registering clock driver specifications pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
temperature sensor with serial presence-detect eeprom the temperature sensor continuously monitors the module's temperature and can be read back at any time over the i 2 c bus shared with the spd eeprom. serial presence-detect for the latest spd data, refer to micron's spd page: www.micron.com/spd . table 12: temperature sensor with spd eeprom operating conditions parameter/condition symbol min max units supply voltage v ddspd 3.0 3.6 v supply current: v dd = 3.3v i dd C 2.0 ma input high voltage: logic 1; scl, sda v ih 1.45 v ddspd + 1 v input low voltage: logic 0; scl, sda v il C 0.55 v output low voltage: i out = 2.1ma v ol C 0.4 v input current i in C5.0 5.0 a temperature sensing range C C40 125 c temperature sensor accuracy (class b) C C1.0 1.0 c table 13: temperature sensor and eeprom serial interface timing parameter/condition symbol min max units time bus must be free before a new transition can start t buf 4.7 C s sda fall time t f 20 300 ns sda rise time t r C 1000 ns data hold time t hd:dat 200 900 ns start condition hold time t h:sta 4.0 C s clock high period t high 4.0 50 s clock low period t low 4.7 C s scl clock frequency t scl 10 100 khz data setup time t su:dat 250 C ns start condition setup time t su:sta 4.7 C s stop condition setup time t su:sto 4.0 C s event# pin the temperature sensor also adds the event# pin (open-drain). not used by the spd eeprom, event# is a temperature sensor output used to flag critical events that can be set up in the sensors configuration register. event# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. the open-drain output of event# under the three separate operating modes is illustrated below. event thresholds are programmed in the 0x01 reg- ister using a hysteresis. the alarm window provides a comparison window, with upper 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
and lower limits set in the alarm upper boundary register and the alarm lower boun- dary register, respectively. when the alarm window is enabled, event# will trigger whenever the temperature is outside the min or max values set by the user. the interrupt mode enables software to reset event# after a critical temperature thresh- old has been detected. threshold points are set in the configuration register by the user. this mode triggers the critical temperature limit and both the min and max of the tem- perature window. the compare mode is similar to the interrupt mode, except event# cannot be reset by the user and returns to the logic high state only when the temperature falls below the programmed thresholds. critical temperature mode triggers event# only when the temperature has exceeded the programmed critical trip point. when the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical event# cannot be cleared through software. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm temperature sensor with serial presence-detect eeprom pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.
module dimensions figure 3: 240-pin ddr3 rdimm 19.6 (0.772) 19.4 (0.764) pin 1 2.5 (0.098) d (2x) 2.3 (0.091) typ 5.0 (0.197) typ 123.0 (4.84) typ 1.0 (0.039) typ 0.8 (0.031) typ 0.75 (0.03) r (6x) 0.76 (0.03) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 47.0 (1.85) typ 71.0 (2.79) typ 9.5 (0.374) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 4.0 (0.157) max 2.2 (0.087) typ 1.45 (0.057) typ 3.05 (0.12) typ 54.68 (2.15) typ 3.0 (0.118) x4 typ u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 1.37 (0.054) 1.17 (0.046) 9.1 (0.358) max with heat spreader attached u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. twindie is a trademark of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 8gb (x72, ecc, dr) 240-pin ddr3 sdram rdimm module dimensions pdf: 09005aef8333011d jc-z-s36c1gx72py.pdf - rev. e 8/10 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2008 micron technology, inc. all rights reserved.

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